Dynamic random access memories (DRAM's) are used in many computer applications, for example in conjunction with cache memories that are incorporated into high performance central processing units.
Typical previously known DRAM's are internally organized so as to provide a narrow data word of only a few bits wide, for example typical width of the data word provided is only one or four bits, while providing a wide memory address word that is sufficient for addressing a typical memory depth of a million or more data words.
In cache memory applications, main memory is organized in an entire cache line that is many bits wide and that is accessed at one time. Accordingly, a plurality of DRAM packages each providing a narrow data word are used in parallel, so as to build up a combined data word having sufficient width for the entire cache line.
For example, as shown in FIG. 1 of the prior art, a central processing unit (CPU) 101 reads data from and writes data into a plurality of packaged DRAM's 111 arranged in parallel to provide a memory. The CPU 101 provides a read or write address to a CPU address bus 105 and further provides a CPU status signal 103 to instruct previously known system logic 106 to read/write the data from/into the packaged DRAM's 111. The system logic 106 transmits the address provided from the CPU address bus 105 onto a memory address bus 107 as a row address and a column address of the packaged DRAM's.
The packaged DRAM's each have a group of address pins electrically coupled to the memory address bus 107 and further have a separate group of data pins electrically coupled to the CPU data bus 102. The system logic 106 further employs a row-address-strobe (RAS) signal 108 for synchronizing a row address provided to the packaged DRAM's. Thereafter, the system logic 106 employs a column-address-strobe (CAS) signal 109 for synchronizing a row address provided to the packaged DRAM's.
At that time, if the CPU status signal 103 from the CPU 101 is an instruction to write associated data into the packaged DRAM's, a write enable (WE) signal 110 synchronizes transferring the write data on the CPU data bus 102, provided from the CPU 101, into the packaged DRAM's 111 through the data pins.
In contrast, if the CPU status signal 103 form the CPU 101 is an instruction to read associated data from the packaged DRAM's, then after a short delay, data from the packaged DRAM's is outputted on the CPU data bus 102 through the data pins and is received by the CPU 101. The system logic 106 coordinates the timing of the receiving of the read data by the CPU 101 by using a ready signal 104.
One reason why packaged DRAM's generally have narrow data words is that using typical previously known DRAM architectures to provide wider data words would require more electrical connections to data pins, which are an expensive resource for each packaged DRAM.
While previously known architectures for packaged DRAM's provide some advantages, some limitations still remain. In previously known DRAM architectures that use separate electrical connections for data and address, address pins are not available for transferring data, and data pins are not available for transferring addresses.
What is needed is a memory architecture that provides wide data words up to the width of the address word or wider than the address word, without requiring separate groups of electrical contacts for data and address.